Chinese Chipmakers Push DUV Limits at Rising Cost

Chinese semiconductor manufacturers are using older deep ultraviolet equipment to produce advanced chips. They do this by exposing the silicon wafers multiple times. This method allows them to bypass the ban on extreme ultraviolet machines. The process works, but it comes with significant financial and technical penalties. Experts say the approach increases the chance of defects. It also lengthens production times and raises costs.

The restriction on EUV lithography is a major hurdle for China. ASML is the sole provider of these machines. They use light with a 13.5 nanometer wavelength to print fine features. Analysts estimate the technology gap between China and the West is at least five years. This disparity affects the speed at which Chinese firms can develop cutting-edge processors. The reliance on older tools shapes the entire strategy of local chipmakers.

China has achieved more progress than many predicted. A teardown of the Huawei Mate 60 Pro in 2023 revealed its processor. The Kirin 9000S was made by SMIC without EUV. It used a second-generation 7nm class process. Recent analysis of the Kirin 9030 shows further advancement. SMIC has moved its DUV based process closer to 5nm density. It still lags behind TSMC and Samsung in leading processes. The company continues to close the performance gap.

The core technique is multiple patterning. Instead of one pass, makers split designs into simpler patterns. They build the intended layer step by step. Chris Mack of Fractilia notes that the cost trade-offs are often ignored. Industry wisdom suggests three exposures on a 193 immersion tool cost about the same as one EUV pass. At four masks, EUV becomes the cheaper option. This economic threshold limits how far DUV can be pushed profitably.

Quality control becomes a major issue with multiple exposures. Each new pattern must align perfectly with the previous one. More passes lead to accumulated overlay errors. Designers must add space around features to compensate. This enlarges the chip and reduces the number of dies per wafer. Wafers cost tens of thousands of dollars each. Mack emphasizes that manufacturers sell dies, not wafers. Larger chips mean fewer sellable units from the same material.

Memory production highlights the efficiency gap. Morgan Stanley reported in June that CXMT produces less output. Chinese DRAM maker CXMT yields only about one-third as many bits per wafer as Western rivals. The bank called lithography access a hard ceiling for memory development. Mack notes that node labels like 5nm have limited meaning on their own. SMIC's N+3 process is progress but remains less scaled than established 5nm nodes from Samsung and TSMC.

DUV technology still has potential for further development. Micron developed its 1-alpha DRAM without using EUV. It relied on multiple patterning and tight process control. Mack stated that Micron pushed 193 immersion farther than other memory makers. Morgan Stanley believes CXMT can reach 1-alpha DRAM without EUV. Douglas Fuller from Copenhagen Business School expects advanced packaging to help. He predicts DUV will be used for the latest DRAM generations by the end of the decade.

However, EUV remains necessary for the most advanced nodes. Micron eventually used EUV for its 1-gamma DRAM. This generation offers more than 30% greater bit density per wafer than the previous 1-beta version. EUV has its own issues, such as stochastic effects. These can be countered with higher exposure doses, which increases cost. Mack says it is hard to believe 3nm or 2nm nodes are economically viable without EUV. The technology is essential for future scaling.

Chinese chipmakers will continue to advance despite the constraints. They can push DUV further by accepting larger dies and poorer yields. They may also face longer manufacturing times. Firms can add capacity to offset these inefficiencies. Morgan Stanley projects CXMT will stay on 1-alpha without EUV. The bank expects CXMT's share of global DRAM bit supply to rise from 14% in 2026 to 16% in 2028. China's AI chip self-sufficiency is expected to grow from 42% in 2025 to 70% by 2030. Gaps in EUV, HBM, and advanced software will persist.